The IEEE Journal of the Electron Devices Society has published an article titled:
Best Practices for Compact Modeling in Verilog-A
The article is freely available for download via open access. It covers how to avoid many of the pitfalls in using Verilog-A compact modeling. It is unclear if this might be related to the effort described in our previous post.
One of the other sites I manage is TCAD Central – https://www.tcadcentral.com. It is a resource concerning TCAD and semiconductor device simulation. Some of the content is no longer current. Please let me know if you have any updates or news in this blog or on the TCAD Central site.
I’ve started a new website at https://www.tcadcentral.com. It is a wiki dedicated to technology computer aided-design. Please check it out, and let me know if you have suggestions, or would like to participate.