Sponsored Master’s Thesis Research in TCAD


Master thesis: Development of automated TCAD tools for the assessment of electro migration in highly integrated circuits

Advertising institute: ZEA-2 – Electronic Systems
Reference number: D127/2016, Electrical engineering, physics
The Central Institute of Engineering, Electronics and Analytics (ZEA-2 – Electronic Systems) is a scientific technical institute of Forschungszentrum Jülich GmbH performing research and development projects in cooperation with the institutes of the research center as well as external partners. The focus of our work is electronic and information technology system solutions in sensor and detektor technology, signal and data processing as well as measurement techniques.

More information available here

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Coventor Adds RC Extraction Capability

EETimes reports that Coventor has added RC Extraction and other analysis features to their SEMulator3D process emulation software. This brings their tool in more direct competition with traditional TCAD. This is in contrast to their past blog postings which attempt to differentiate themselves from traditional process simulation and TCAD tools.

Process Simulation vs. Process Emulation: is SEMulator3D really TCAD?

Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation

It will be interesting to see if their work with Gold Standard Simulations continues, now that the TCAD company has been acquired by Synopsys.

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Synopsys Acquires Gold Standard Simulations

From http://www.prnewswire.com/news-releases/synopsys-completes-acquisition-of-gold-standard-simulations-300273214.html:

MOUNTAIN VIEW, Calif., May 23, 2016 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS) today announced it has completed the acquisition of Gold Standard Simulations Ltd. (GSS), a leading provider of TCAD and EDA simulation solutions for design technology co-optimization (DTCO) of advanced process nodes. The acquisition of GSS supports the Synopsys TCAD strategy to offer a comprehensive solution to reduce development time and cost for advanced node development by enabling the evaluation and selection of process, device and materials options in the pre-wafer research phases of development. The terms of the deal, which is not material to Synopsys financials, are not being disclosed.

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Semiconductor Device Simulation Using DEVSIM

Semiconductor Device Simulation Using DEVSIM is now available from our site.

Abstract:
DEVSIM is a technology computer aided design (TCAD) simulation software. It is released under an open source license. The software solves user defined partial differential equations (PDEs) on 1D, 2D, and 3D meshes. It is implemented in C++ using custom code and a collection of open source libraries. The Python scripting interface enables users to setup and control their simulations.

In this chapter, we present an overview of the tool. This is followed with a bipolar junction transistor (BJT) design and characterization example. A collection of open source tools were used to create a simulation mesh, and visualize results

The Python scripts for simulation are here:
https://github.com/devsim/devsim_bjt_example

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DEVSIM under new open source license

The DEVSIM source code is now released under the Apache License, Version 2.0. It was previously under the LGPL 3.0. The license change is intended to promote adoption of the software and attract new contributors. A brief synopsis of the license is here.

The spirit of the Apache License is also more in line with the license terms packages that DEVSIM relies upon. More information about DEVSIM is available from http://www.devsim.org.

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Cogenda Genius Open Source Update

Cogenda has updated the open source repository for the Genius Semiconductor Device Simulator. This is the first update to the open source project in 3 years. The commit message states that this update synchronizes the software with the 1.9.0 version of their commercial tool. The code distribution is on GitHub.

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Verilog A Best Practices Paper

The IEEE Journal of the Electron Devices Society has published an article titled:
Best Practices for Compact Modeling in Verilog-A

The article is freely available for download via open access. It covers how to avoid many of the pitfalls in using Verilog-A compact modeling. It is unclear if this might be related to the effort described in our previous post.

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VALint: the NEEDS Verilog-A Checker

An interesting project on nanoHUB is a Verilog-A checker, VALint.

From their abstract

VALint is the NEEDS created, automatic Verilog-A code checker. Its purpose is to check the quality of the Verilog-A code and provide the author feedback if bad practices, common mistakes, pitfalls, or inefficiencies are found.

It is currently in beta. We hope that this project is successful as Verilog-A is the language for sharing compact models between researchers and circuit simulator software companies. The project is open source and can be downloaded. It can also be launched on nanoHUB on their online simulation platform.

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TCAD Central

One of the other sites I manage is TCAD Central – http://www.tcadcentral.com. It is a resource concerning TCAD and semiconductor device simulation. Some of the content is no longer current. Please let me know if you have any updates or news in this blog or on the TCAD Central site.

If you have any announcements concerning TCAD companies, modeling, or simulation, please send us a note via the contact form.